Performance Modelling and High Performance Buffer Design for the System with Network on Chip

by Jin Liu, Ph.D. Washington State University DECEMBER 2007 Chair: José G. Delgado-Frias High performance novel dynamically allocated multi-queue (DAMQ) buffer schemes for systems with network on chip (NoC) have been proposed and evaluated in this dissertation. An analytical model to predict performance of a NoC where wormhole switching technique and fully adaptive routing protocols has been developed and compared with simulations. In this dissertation, a novel analytical model for NoC which makes use of simple close form calculations is presented. This model provides accurate network performance prediction in the network stable region. The validity of this model is demonstrated by comparing analytical prediction with simulation results obtained on high-radix k-ary 2-cube networks. Three novel switch buffer schemes, DAMQall, DAMQmin and DAMQshared, for system on chip with an interconnection network are also reported. The proposed schemes are based on a DAMQ self-compacting buffer hardware design. These schemes outperform existing approaches. DAMQall have similar performance using only half of the buffer size used in traditional SAMQ implementations. DAMQmin provides an excellent approach to optimize buffer management providing a good throughput when the network has a larger load. DAMQshared scheme lets virtual channels from different physical channel share free buffer space. While providing similar performance, DAMQshared scheme uses only around sixty percent of the buffer size that is used in